1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly to a semiconductor memory device having an improved access time, decreased power consumption and enhanced reliability by providing hierarchical row-selecting lines and word lines therein.
2. Description of the Background Art
FIG. 1 is a block diagram illustrating a first example of a conventional semiconductor memory device. Referring to the figure, row address data is externally applied to a row address input terminal group 1 to be amplified or inverted by a row address buffer 2, and then applied to a row address decoder 3. The row address decoder 3 decodes a row address data applied via the input terminal group 1.
Column address data is externally applied to a column address input terminal group 4 to be amplified or inverted by a column address buffer 5, and then applied to a column address decoder 6. The column address decoder decodes a column address data applied via the input terminal group 4. A memory cell array 7 is formed of a plurality of memory cells arranged in matrix for storing information. A read voltage with a small amplitude read from the memory cell array 7 via a multiplexer 8 is sensed and amplified by a sense amplifier 9. An output of the sense amplifier 9 is further amplified by an output data buffer 10 to a required level that the output is extracted to the outside of the semiconductor memory device, and then is externally outputted via a read data output terminal 11.
Write data is applied to a write data input terminal 12 to be amplified by an input data buffer 13. Further, a terminal 14 is supplied with a chip select input, while a terminal 15 is supplied with a read/write control input. A read/write control circuit 16 controls the sense amplifier 9, the output data buffer 10 and the input data buffer 13 in accordance with selection/non-selection of a chip and data read/write mode, determined by these inputs.
FIG. 2 is a diagram illustrating a configuration of the periphery of the memory cell array 7 in the semiconductor memory device shown in FIG. 1. The figure shows, for simplification, a double-row and double-column configuration of the memory cell array 7.
As shown in FIG. 2, memory cells 24a-24d are provided at the intersections of respective bit line pairs 20a, 20b and 21a, 21b and respective word lines 22 and 23 connected to output points of the row address decoder 3. In addition, a plurality of bit line loads 25a, 25b, 26a and 26b are provided having their respective one ends connected to a power source 18 and the other ends connected to their corresponding bit lines. Further, transfer gates 27a, 27b, 28a and 28b constituting the multiplexer 8 in FIG. 1 are provided, each having its gate supplied with an output signal of the column address decoder 6 in FIG. 1, its drain or source connected to its corresponding bit line, and its source or drain connected to a corresponding one of input/output lines (hereinafter referred to as I/O lines) 29a, 29b in a pair. A potential difference between the I/O lines 29a and 29b is detected by the sense amplifier 9, and an output thereof is amplified by the output buffer 10.
For each of the memory cells 24 in FIG. 2, for example, a high resistance load-type NMOS memory cell shown in FIG. 3A or a CMOS-type memory cell as shown in FIG. 3B is employed.
The memory cell 24 shown in FIG. 3A comprises driver transistors 41a and 41b. The transistor 41a has its drain connected to a storage node 45a, its gate connected to a storage node 45b and its source grounded. The transistor 41b has its drain connected to the storage node 45b, its gate connected to the storage node 45a and its source grounded. Furthermore, the memory cell 24 comprises access transistors 42a and 42b. The transistor 42a has its drain or source connected to the storage node 45a, its gate connected to the word line 22 or 23 and its source or drain connected to the bit line 20a or 21a. The transistor 42b has its drain or source connected to the storage node 45b, its gate connected to the word line 22 or 23 and its source or drain connected to the bit line 20b or 21b. Moreover, the memory cell 24 comprises load resistors 43a and 43b having their respective ends connected to the power source 18 and the other ends connected to the respective storage nodes 45a and 45b.
Meanwhile, the memory cell 24 shown in FIG. 3B comprises p channel transistors 44a and 44b in place of the load resistors 43a and 43b of the memory cell 24 in FIG. 3A. The transistor 44a has its drain connected to the storage node 45a, its gate connected to the storage node 45b and its source connected to the power source 18. The transistor 44b has its drain connected to the storage node 45b, its gate connected to the storage node 45a and its source connected to the power source 18.
An operation in the conventional example shown in FIG. 1 to FIG. 3 will now be described. Such case is considered that the memory cell 24a in the memory cell array 7 is selected. In this case, a row address data corresponding to a row, to which the memory cell 24a to be selected is coupled, is inputted from the row address input terminal group 1, so that the word line 22 connected to the memory cell 24a attains a selection level (e.g., logical high or the H level), while the other word line 23 attains a non-selection level (e.g., logical low or the L level). Meanwhile, a column address data for selecting a column corresponding to the bit line pair 20a, 20b connected to the memory cell 24a to be selected is inputted from the column address input terminal group 4, so that the transfer gates 27a and 27b connected to the bit line pair 20a, 20b are only rendered conductive. As a result, the selected bit lines 20a and 20b are only connected to the I/O line pair 29a, 29b, respectively, while the other bit lines 21a and 21b become a non-selection state to be separated from the I/O line pair 29a, 29b.
A read operation of the selected memory cell 24a will now be described. It is now assumed that the storage node 45a of the memory cell 24a is at the H level, and the storage node 45b is at the L level. At this time, the driver transistor 41a in the memory cell is not conductive, while the other driver transistor 41b is conductive. Further, since the word line 22 is at the selection state at the H level, the access transistors 42a and 42b of the memory cell 24a are both conductive. Therefore, a direct current flows through such a path as the power source 18.fwdarw.the bit line load 25b.fwdarw.the bit line 20b.fwdarw.the access transistor 42b.fwdarw.the driver transistor 41b.fwdarw.the ground. However, since the driver transistor 41a is not conductive, the direct current does not flow through the other path such as the power source 18.fwdarw.the bit line load 25a.fwdarw.the bit line 20a.fwdarw.the access transistor 42a.fwdarw.the driver transistor 41a.fwdarw.the ground. At this time, a potential on the bit line 20a, through which the direct current does not flow, becomes (a supply potential - Vth) if threshold voltages of the bit line load transistors 25a, 25b, 26a and 26b are Vth. Furthermore, a potential on the bit line 20b, through which the direct current flows, is divided by conductive resistances of the driver transistor 41b, the access transistor 42b and the bit line load 25b, and consequently, the potential decreases by .DELTA.V from the value of (the supply potential - Vth) to be the value of (the supply potential - Vth-.DELTA.V). The .DELTA.V is called a bit line amplitude, which is normally about 50 mV-500 mV and is controlled depending on the magnitude of the bit line load.
This bit line amplitude appears on the I/O lines 29a and 29b through the conductive transfer gates 27a and 27b to be amplified by the sense amplifier 9. After further amplified in the output buffer 10, the bit line amplitude is read from the output terminal 11 as a data output. In reading, the input data buffer 13 is controlled by the read/write control circuit 16 so as not to drive the I/O line pair 29a, 29b.
Meanwhile, in writing, the potential on the bit line, in which data of the L level is to be written, is forced to be lowered to a lower potential, and the potential on the other bit line is raised to a higher potential, thereby carrying out data writing in the memory cell. For writing inverted data in the memory cell 24a, for example, the data input buffer 13 makes the I/O line 29a be at the L level and the other I/O line 29b be at the H level. Accordingly, the bit line 20a goes to the L level and the other bit line 20b goes to the H level, and thus the data is written.
Since the conventional semiconductor memory device is configured as described above, all the memory cells in the same row are activated to let a current flow therein from the power source, whereby there has been a disadvantage, especially in the configuration of a large capacity semiconductor memory device, that current consumption increases throughout the device.
Furthermore, in the large capacity semiconductor memory device, an increase in length of a word line causes an increase in resistance of the word line, as a whole, formed of such as polysilicon, molybdenum silicide or tungsten silicide having higher resistance than a metal, and furthermore, the increased number of the memory cells connected to the same word line causes an increased capacitive load. Consequently, a delay time on the word line is increased, resulting in another disadvantage that a high speed access cannot be performed.
In order to eliminate these disadvantages, a second conventional example of the semiconductor memory device is proposed as shown in FIG. 4, which is, for example, disclosed in Japanese Patent Laying Open No. 58-211393 and the U. S. Pat. No. 4,542,486. This semiconductor memory device comprises N memory cell groups formed by dividing in a column direction a memory cell array formed of memory cells arranged in matrix, memory cell group selecting lines for each selecting the corresponding one of the N memory cell groups, row decoders for each decoding a row address signal of the memory cell group to be accessed, preceding word lines each connected to an output terminal of the corresponding one of the row decoders, AND function gates for each taking a logical product of a selecting signal on the memory cell group selecting line and an output signal on the preceding word line, and word lines connected to output terminals thereof. The preceding word lines and the latter word lines are arranged in parallel to each other in a row direction.
FIG. 4 shows as one example of the described semiconductor memory device, the case that the memory cell array is divided into N (3) blocks in the column direction to form N (3) memory cell groups 51a-51c.
Referring to FIG. 4, memory cell group selecting lines 52a-52c select corresponding memory cell groups 51a-51c, respectively. A plurality of preceding word lines 55 are connected to outputs of row decoders 54 and are arranged in parallel in one direction. Furthermore, a plurality of AND function gates 56a-56c are provided with their inputs connected to the preceding word lines 55 and the memory cell group selecting lines, respectively. Word lines 53a-53c are connected to the respective outputs of these gates.
An operation of a second conventional example of this semiconductor memory device will now be described. As shown in FIG. 4, the word line 53a in the memory cell group 51a, for example, is activated by a switching gate 56a receiving as its inputs a signal on the preceding word line 55 as a row-selecting line and a signal on the memory cell group selecting line 52a running vertically to the preceding word line 55. In the device of FIG. 4, the time to select a particular row is determined by a delay time on the preceding word line 55 and that on the word line 53a.
A capacitance of the preceding word line 55 does not include a gate capacitance which is the sum of the gate-drain capacitance, gate-source capacitance and gate-substrate capacitance of the respective access transistors 42a and 42b in each of the memory cells, so that the capacitance of the preceding word line 55 is considerably smaller than a capacitance of a conventional word line including these capacitances. Furthermore, the word line 53a is short such that CR delay thereon can be ignored. Therefore, the time to select the row can substantially be reduced compared to the conventional by employing this second conventional example.
In addition, since the preceding word line 55 does not constitute a gate electrode, a material of the preceding word line 55 as the row-selecting line can be selected irrelevant to a work function and can further employ various low resistance materials.
Moreover, only the memory cell connected to a single word line 53a in the selected memory cell group are only accessed, in this second conventional example, so that an ineffective current flowing into the memory cells from the load transistors of the bit lines can be reduced to the amount of 1/(the number of blocks) compared to the conventional, and thus power consumption can be reduced at the same time.
However, since the semiconductor memory device according to the second conventional example is configured as aforementioned, the number of AND function gates 56 connected to a single preceding word line 55 increases and also the length of the preceding word line 55 itself increases in a larger capacity semiconductor memory device, in which a memory cell array need be divided into a large number of blocks for lower power consumption. Accordingly, there was a disadvantage that capacitance and resistance of the preceding word line 56 increase so that a delay on the preceding word line 55 increases.
Furthermore, since the large capacity semiconductor memory device requires a large number of divided blocks of the memory cell array for lower power consumption as described above, the capacitance of the preceding word line 55 is increased, and thus a MOS transistor of the row decoder 54 for driving the preceding word line 55 operates in a saturation region over a long period of time. As a result, a problem in reliability of the semiconductor memory device arose as follows: Due to an effect so-called a hot electron effect that an intensity of an electric field is increased in a channel region of a miniaturized MOS transistor to let electrons flow in a gate oxide film, thereby raising a threshold value of the transistor, a threshold voltage of the MOS transistor fluctuates in time and thus the access time in the semiconductor memory device shifts. Therefore due to this disadvantage as pointed out above, it is impossible in the large capacity semiconductor memory device that the memory cell array is divided into multi-blocks.
In addition, another problem arose in reliability of the large capacity semiconductor memory device that due to increased capacitance of the preceding word line 55 which causes an increased charge/discharge current to flow through the word line 55, migration of aluminum and then a disconnection occur particularly in the case of the preceding word line formed of aluminum metal.